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ds07-13703-2e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90540/545 series mb90f543/f549/v540 n n n n description the mb90540/545 series with full-can* 1 and flash rom is specially designed for automotive and industrial ap- plications. its main features are two on board can interfaces (one for mb90v545 series), which conform to v2.0 part a and part b, supporting very flexible message buffer scheme and so offering more functions than a normal full can approach. the instruction set by f 2 mc-16lx cpu core inherits an at architecture of the f 2 mc* 2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division in- structions, and enhanced bit manipulation instructions.the micro controller has a 32-bit accumulator for processing long word data.the mb90540/545 series has peripheral resources of 8/10-bit a/d converters, uart(sci), extended i/o serial interfaces, 8/16-bit timer, i/o timer (input capture(icu), output compare (ocu)). *1:controller area network (can) - license of robert bosch gmbh. *2:f 2 mc stands for fujitsu flexible microcontroller. n n n n features ?clock embedded pll clock multiplication circuit operating clock (pll clock) can be selected from: divided-by-2 of oscillation or one to four times the oscillation minimum instruction execution time: 62.5 ns (operation at oscillation of 4 mhz, four times the oscillation clock, v cc of 5.0v) subsystem clock: 32 khz (continued) n n n n pac k ag e 100-pin plastic qfp (fpt-100p-m06)
mb90540/545 series 2 (continued) ? instruction set to optimize controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) enhanced signed multiplication/division instruction and reti instruction functions enhanced precision calculation realized by the 32-bit accumulator ? instruction set designed for high level language (c language) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? program patch function (for two address pointers) ? enhanced execution speed: 4-byte instruction queue ? enhanced interrupt function: 8 levels, 34 factors ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os) ? embedded rom size and types flash rom: 128 kbytes / 256 kbytes embedded ram size: 6 kbytes / 8 kbytes (evaluation chip) ?flash rom supports automatic programming, embedded algorithm tm* write / erase / erase-suspend / resume commands a flag indicating completion of the algorithm hard-wired reset vector available in order to point to a fixed boot sector in flash memory erase can be performed on each block block protection with external programming voltage ? low-power consumption (stand-by) mode sleep mode (mode in which cpu operating clock is stopped) stop mode (mode in which oscillation is stopped) cpu intermittent operation mode clock mode hardware stand-by mode ?process 0.5 m m cmos technology ? i/o port general-purpose i/o ports: 81 ports ?timer watchdog timer: 1 channel 8/16-bit ppg timer: 8/16-bit 4 channels 16-bit re-load timer: 2 channels ? 16-bit i/o timer 16-bit free-run timer: 1 channel input capture: 8 channels output compare: 4 channels ? extended i/o serial interface: 1 channel ?uart 0 with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. (continued)
mb90540/545 series 3 (continued) ?uart 1 with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized serial (extended i/o serial) can be used. ? external interrupt circuit (8 channels) a module for starting an extended intelligent i/o service (ei 2 os) and generating an external interrupt which is triggered by an external input. ? delayed interrupt generation module generates an interrupt request for switching tasks. ? 8/10-bit a/d converter (8 channels) 8/10-bit resolution can be selectively used. starting by an external trigger input. conversion time: 26.3 m s ? full-can interfaces mb90540 series: 2 channel mb90545 series: 1 channel conforming to version 2.0 part a and part b flexible message buffering (mailbox and fifo buffering can be mixed) ? external bus interface: maximum address space 16 mbytes *: embedded algorithm is a trade mark of advanced micro devices inc.
mb90540/545 series 4 n n n n product lineup the following table provides a quick outlook of the mb90540/545 series (continued) features mb90f543 mb90f549 mb90v540 classification flash rom product evaluation product rom size 128 kbytes boot block 256 kbytes boot block none rom size 6 k 8 k cpu functions the number of instructions: 351 instruction bit length: 8 bits, 16 bits instruction length: 1 byte to 7 bytes data bit length: 1bit, 8 bits, 16 bits minimum execution time: 62.5 ns (at machine clock frequency of 16 mhz) interrupt processing time: 1.5 m s (at machine clock frequency of 16 mhz, minimum value) uart 0 clock synchronized transmission (500 k / 1m / 2 mbps) clock asynchronized transmission (4808 / 5208 / 9615 / 10417 / 19230 / 38460 / 62500 /500000 bps at machine clock frequency of 16 mhz) transmission can be performed by bi-directional serial transmission or by master/slave connection. uart 1 (sci) clock synchronized transmission (62.5 k/ 12 k/ 250 k/ 500 k/ 1 mbps) clock asynchronized transmission (1202/ 2404/ 4808/ 9615/ 31250 bps) transmission can be performed by bi-directional serial transmission or by master / slave connection. 8/10-bit a/d converter conversion precision: 8/10-bit can be selectively used. number of inputs: 8 one-shot conversion mode (converts selected channel once only) scan conversion mode (converts two or mode successive channels and can program up to 8 channels) continuous conversion mode (converts selected channel continuously) stop conversion mode (converts selected channel and stop operation repeatedly) 8/16-bit ppg timers number of channels: 8/16 bit 4 channels ppg operation of 8-bit or 16 bit a pulse wave of given intervals and given duty ratios can be output. pulse interval: fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , 128 m s (at oscillation of 4 mhz, fsys = machine clock frequency of 16 mhz, fosc = oscillation clock frequency) 16-bit reload timer number of channels:2 operation clock frequency: fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = system clock frequency) supports external event count function 16-bit i/o timer 16-bit output com- pares number of channels: 4 pin input factor: a match signal of compare register input cap- tures number of channels: 8 rewriting a register value upon a pin input (rising, falling, or both edges)
mb90540/545 series 5 (continued) *: varies with conditions such as operating frequency. (see section n electrical characteristics.) features mb90f543 mb90f549 mb90v540 can interface number of channels: 2(mb90540 series), 1(mb90545 series) conforms to can specification version 2.0 part a and b automatic re-transmission in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and ids supports multiple messages flexible configuration of acceptance filtering: full bit compare / full bit mask / two partial bit masks supports up to 1 mbps external interrupt cir- cuit number of inputs: 8 started by a rising edge, a falling edge, an h level input, or an l level input. extended i/o serial interface clock synchronized transmission (31.25 k / 62.5 k /125 k / 500 k / 1 mbps at machine clock frequency of 16 mhz) lsb first / msb first watchdog timer reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 mhz, minimum value) flash memory supports automatic programming, embedded algorithm tm and write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm hard-wired reset vector available in order to point to a fixed boot sector in flash memory boot block configuration erase can be performed on each block block protection with external programming voltage flash writer from minato electronics inc. low-power consump- tion (stand-by) mode sleep/ stop/ cpu intermittent operation/ clock timer/ hardware stand-by process cmos power supply voltage for operation 5 v 10 % package qfp-100 pga-256
mb90540/545 series 6 n n n n pin assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vss p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 vcc x1 x0 p10/ad08 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 9 8 md1 md0 p57/tot0 p56/tin0 p67/an7 p66/an6 p65/an5 p64/an4 vss p63/an3 p62/an2 p61/an1 p60/an0 avss avrl avrh avcc p55/adtg p54/int7 p53/int6 x0a x1a pa 0 rst p97/rx1 p96/tx1 p95/rx0 p94/tx0 p93/int3 p92/int2 p91/int1 p90/int0 p87/tot1 p86/tin1 p85/out1 p84/out0 p83/ppg3 p82/ppg2 p81/ppg1 p80/ppg0 p77/out3/in7 p76/out2/in6 p75/in5 p74/in4 p73/in3 p72/in2 p71/in1 p70/in0 hst md2 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd p52/int5 p51/int4 p50/sin2 c p47/sck2 p46/sot2 p45/sot1 vcc p44/sck1 p43/sin1 p42/sin0 p41/sck0 p40/sot0 p37/clk p36/rdy p35/hak p34/hrq p33/wrh p32/wrl /wr vss (top view) (fpt-100p-m06) (continued)
mb90540/545 series 7 n n n n pin description no. pin name circuit type function 82 83 x0 x1 a (oscillation) high speed oscillator input pins 80 79 x0a x1a a (oscillation) low speed oscillator input pins 77 rst b external reset request input 52 hst c hardware standby input 85 to 92 p00 to p07 i general i/o port with programmable pullup. this function is enabled in the single-chip mode. ad00 to ad07 i/o pins for 8 lower bits of the external address/data bus. this func- tion is enabled when the external bus is enabled. 93 to 100 p10 to p17 i general i/o port with programmable pullup. this function is enabled in the single-chip mode. ad08 to ad15 i/o pins for 8 higher bits of the external address/data bus. this func- tion is enabled when the external bus is enabled. 1 to 8 p20 to p27 h general i/o port with programmable pullup. this function is enabled in the single-chip mode. a16 to a23 8-bit i/o pins for a16 to a23 at the external address bus. this func- tion is enabled when the external bus is enabled. 9 p30 i general i/o port with programmable pullup. this function is enabled in the single-chip mode. ale address latch enable output pin. this function is enabled when the external bus is enabled. 10 p31 i general i/o port with programmable pullup. this function is enabled in the single-chip mode. rd read strobe output pin for the data bus. this function is enabled when the external bus is enabled. 12 p32 i general i/o port with programmable pullup. this function is enabled in the single-chip mode or when the wr /wrl pin output is disabled. wrl write strobe output pin for the data bus. this function is enabled when both the external bus and the wr /wrl pin output are en- abled. wrl is write-strobe output pin for the lower 8 bits of the data bus in 16-bit access. wr is write-strobe output pin for the 8 bits of the data bus in 8-bit access. wr 13 p33 i general i/o port with programmable pullup. this function is enabled in the single-chip mode or external bus 8-bit mode or when wrh pin output is disabled. wrh write strobe output pin for the 8 higher bits of the data bus. this function is enabled when the external bus is enabled, when the ex- ternal bus 16-bit mode is selected, and when the wrh output pin is enabled. (continued)
mb90540/545 series 8 14 p34 i general i/o port with programmable pullup. this function is enabled in the single-chip mode or when the hold function is disabled. hrq hold request input pin. this function is enabled when both the exter- nal bus and the hold functions are enabled. 15 p35 i general i/o port with programmable pullup. this function is enabled in the single-chip mode or when the hold function is disabled. hak hold acknowledge output pin. this function is enabled when both the external bus and the hold functions are enabled. 16 p36 i general i/o port with programmable pullup. this function is enabled in the single-chip mode or when the external ready function is dis- abled. rdy ready input pin. this function is enabled when both the external bus and the external ready functions are enabled. 17 p37 h general i/o port with programmable pullup. this function is enabled in the single-chip mode or when the clock output is disabled. clk clk output pin. this function is enabled when both the external bus and clk outputs are enabled. 18 p40 g general i/o port. this function is enabled when uart0 disables the serial data output. sot0 serial data output pin for uart0. this function is enabled when uart0 enables the serial data output. 19 p41 g general i/o port. this function is enabled when uart0 disables clock output. sck0 clock i/o pin for uart0. this function is enabled when uart0 en- ables the clock output. 20 p42 g general i/o port. this function is always enabled. sin0 serial data input pin for uart0. while uart0 is operating for input, the input of the pin is used as required. except when the function is intentionally used, output from the other functions must be stopped. 21 p43 g general i/o port. this function is always enabled. sin1 serial data input pin for uart1. while uart1 is operating for input, the input of the pin is used as required. except when the function is intentionally used, output from the other functions must be stopped. 22 p44 g general i/o port. this function is enabled when uart1 disables the clock output. sck1 clock pulse input/output pin for uart1. this function is enabled when uart1 enables the clock output. 24 p45 g general i/o port. this function is enabled when uart1 disables the serial data output. sot1 serial data output pin for uart1. this function is enabled when uart1 enables the serial data output. no. pin name circuit type function (continued)
mb90540/545 series 9 25 p46 g general i/o port. this function is enabled when the serial io dis- ables the serial data output. sot2 serial data output pin for the serial io. this function is enabled when the serial io enables the serial data output. 26 p47 g general i/o port. this function is enabled when the serial io dis- ables the clock output. sck2 clock pulse input/output pin for the serial io. this function is en- abled when the serial io enables the clock output. 28 p50 d general i/o port. this function is always enabled. sin2 serial data input pin for the serial io. while the serial io is operating for input, the input of the pin is used as required. except when the function is intentionally used, output from the other functions must be stopped. 29 to 32 p51 to p54 d general i/o port. this function is always enabled. int4 to int7 external interrupt request input pins for int4 to int7. while external interrupt is allowed, the input of the pin is used as required. except when the function is intentionally used, output from the other func- tions must be stopped. 33 p55 d general i/o port. this function is always enabled. adtg trigger input pin for the a/d converter. while the a/d converter is operating for input, the input of the pin is used as required. except when the function is intentionally used, output from the other func- tions must be stopped. 38 to 41 p60 to p63 e general i/o port. this function is enabled when the analog input en- able register specifies a port. an0 to an3 analog input pins for the 8/10-bit a/d converter. this function is en- abled when the analog input enable register specifies ad. 43 to 46 p64 to p67 e general i/o port. the function is enabled when the analog input en- able register specifies a port. an4 to an7 analog input pins for the 8/10-bit a/d converter. this function is en- abled when the analog input enable register specifies ad. 47 p56 d general i/o port. this function is always enabled. tin0 event input pin for the 16-bit reload timers 0. while the 16-bit reload timer is operating for input, the input of the pin is used as required. except when the function is intentionally used, output from the other functions must be stopped. 48 p57 d general i/o port. this function is enabled when the 16-bit reload timers 0 disables the output. tot0 output pin for the 16-bit reload timers 0. this function is enabled when the 16-bit reload timers 0 enables the output. no. pin name circuit type function (continued)
mb90540/545 series 10 53 to 58 p70 to p75 d general i/o ports. this function is always enabled. in0 to in5 data sample input pins for input captures icu0 to icu5. while the icu is for input, the input of the pin is used as required. except when the function is intentionally used, output from the other functions must be stopped. 59 to 60 p76 to p77 d general i/o ports. this function is enabled when the ocu disables the waveform output. out2 to out3 waveform output pins for output compares ocu2 and ocu3. this function is enabled when the ocu enables the waveform output. in6 to in7 data sample input pin for input captures icu6 and icu7. while the icu is for input, the input of the pin is used as required. except when the function is intentionally used, output from the other functions must be stopped. 61 to 64 p80 to p83 d general i/o ports. this function is enabled when 8/16-bit ppg dis- ables the waveform output. ppg0 to ppg3 output pins for 8/16-bit ppgs. this function is enabled when 8/16- bit ppg enables the waveform output. 65 to 66 p84 to p85 d general i/o ports. this function is enabled when the ocu disables the waveform output. out0 to out1 waveform output pins for output compares ocu0 and ocu1. this function is enabled when the ocu enables the waveform output. 67 p86 d general i/o port. this function is always enabled. tin1 event input pin for the 16-bit reload timers 1. while the 16-bit reload timer is operating as an input, the input of the pin is used as re- quired. except when the function is intentionally used, output from the other functions must be stopped. 68 p87 d general i/o port. this function is enabled when the 16-bit reload timers 0 disables the output. tot1 output pin for the 16-bit reload timers 1 this function is enabled when the 16-bit reload timers 1 enables the output. 69 to 72 p90 to p93 d general i/o port. this function is always enabled. int0 to int3 external interrupt request input pins for int0 to int3. while external interrupt is allowed, the input of the pin is used as required. except when the function is intentionally used, output from the other func- tions must be stopped. 73 p94 d general i/o port. this function is enabled when can0 disables the output. tx0 tx output pin for can0. this function is enabled when can0 en- ables the output. 74 p95 d general i/o port. this function is always enabled. rx0 rx input pin for can0 interface. when the can function is used, output from the other functions must be stopped. no. pin name circuit type function (continued)
mb90540/545 series 11 75 p96 d general i/o port. this function is enabled when can1 disables the output. tx1 tx output pin for can1. this function is enabled when can1 en- ables the output (only mb90540 series). 76 p97 d general i/o port. this function is always enabled. rx1 rx input pin for can1 interface. when the can function is used, output from the other functions must be stopped (only mb90540 se- ries). 78 pa0 d general i/o port. this function is always enabled. 34 av cc power supply power supply for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avcc is ap- plied to vcc. 37 av ss power supply power supply for the a/d converter. 35 avrh power supply external reference voltage input for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to avcc. 36 avrl power supply external reference voltage input for the a/d converter. 49 50 md0 md1 c input pins for specifying the operating mode. the pins must be di- rectly connected to vcc or vss. 51 md2 f input pin for specifying the operating mode. the pin must be directly connected to vcc or vss. 27 c this is the power supply stabilization capacitor pin. it should be con- nected externally to an 0.1 m f ceramic capacitor. 23, 84 v cc power supply input pin for power supply (5.0 v) . 11, 42, 81 v ss power supply input pin for power supply (0.0 v) . no. pin name circuit type function (continued)
mb90540/545 series 12 n n n n i/o circuit type circuit type diagram remarks a ? oscillation feedback resistor: 1 m w approx. b ? hysteresis input with pull-up resistor: 50 k w approx. c ? hysteresis input d ? cmos level output ? hysteresis input x1 x0 standby control signal hys r r hys r hys p-ch n-ch v cc r
mb90540/545 series 13 e ? cmos level output ? hysteresis input ? analog input f ? hysteresis input ? pull-down resistor: 50 k w approx. (except flash devices) g ? cmos level output ? hysteresis input ? ttl input (flash devices only) circuit type diagram remarks analog input hys p-ch n-ch v cc r hys r r hys ttl t p-ch n-ch v cc r r
mb90540/545 series 14 h ? cmos level output ? hysteresis input ? programmable pullup resistor: 50 k w approx. i ? cmos level output ? hysteresis input ? ttl level input (flash devices only) ? programmable pullup resistor: 50 k w approx. circuit type diagram remarks cntl hys p-ch n-ch v cc r v cc p-ch cntl hys ttl t p-ch n-ch v cc v cc r r p-ch
mb90540/545 series 15 n n n n handling devices (1) preventing latch-up cmos ic chips may suffer latch-up under the following conditions: ? a voltage higher than vcc or lower than vss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between vcc and vss. ? the avcc power supply is applied before the vcc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. for the same reason, care must also be taken in not allowing the analog power-supply voltage (avcc, avrh, dvcc) to exceed the digital power-supply voltage. (2) handling unused input pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefor they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k w . unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) using external clock to use external clock, drive x0 pin only and leave x1 pin unconnected. below is a diagram of how to use external clock. (4) not using subclock mode oscillations must be connected to the x0a and x1a, even when a subclock is not used. (5) power supply pins (vcc/vss) in products with multiple v cc or v ss pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. however you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via the lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 m f between v cc and v ss pins near the device. x0 x1 mb90540/545 series open vcc vss vss vcc vss vcc mb90540/545 series vcc vss vcc vss
mb90540/545 series 16 (6) pull-up/down resistors the mb90540/545 series does not support internal pull-up/down resistors (except port0 - port3:pull-up resis- tors). use external components where needed. (7) crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via the shortest distances from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board artwork surrounding x0 and x1 pins with a grand area for stabilizing the operation. (8) turning-on sequence of power supply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/off the analog and digital power supplies simulta- neously is acceptable). (9) connection of unused pins of a/d converter connect unused pins of a/d converter to av cc = v cc , av ss = avrh = v ss . (10) n.c. pin the n.c. (internally connected) pin must be opened for use. (11) notes on energization to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 m s or more (0.2 v to 2.7 v). (12) indeterminate outputs from ports 0 and 1 the outputs from 0 and 1 become indeterminate during a power-on reset after the power is turned on. pay attention to the port output timing shown as follows. oscillation setting time *2 step-down circuit setting time *1 vcc(power-supply pin) ponr(power-on reset) signal rst (external asynchronous reset) signal rst(internal reset) signal oscillation clock signal ka(internal operation clock a) signal kb(internal operation clock b) signal port(port output)signal indereterminate period * : 1:step-down circuit setting time : 2 17 /oscillation clock frequency (oscillation clock frequency of 16 mhz: 8.19 ms) * : 2:oscillation setting time: 2 18 /oscillation clock frequency (oscillation cllock frequency of 16 mhz: 16.38 ms) ? timming chart of indeterminate outputs from ports o and 1
mb90540/545 series 17 (13) initialization in the device, there are internal registers which are initialized only by a power-on reset. to initialize these registers, please turn on the power again. (14) directions of div a, ri and divw a, rwi instructions in the signed multiplication and division instructions (div a, ri and divw a, rwi), the value of the corre- sponding bank register (dtb, adb, usb, ssb) is set in 00h. if the values of the corresponding bank registers (dtb,adb,usb,ssb) are set to other than 00h, the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (15) using realos extended intelligent i/o service (ei 2 os) can not be used, while realos is used.
mb90540/545 series 18 n n n n block diagram ram 6 kb rom 128 kb uart0 prescaler sio 1ch prescaler 10-bit adc 8 ch. 16-bit reload timer 2 ch. clock controller can controller 8/16-bit ppg 4 ch. f 2 mc 16lx cpu fmc-16 bus x0,x1 rst hst sot0 sck0 sin0 sot2 sck2 sin2 av cc av ss an0 to an7 avrh avrl adtg ppg[3:0] rx[1:0] tx[1:0] uart1 prescaler sot1 sck1 sin1 (sci) external bus interface ale rd wrl wrh hrq hak rdy clk x0a,x1a /256 kb 16-bit i/o timer 16-bit input capture 8 ch. 16-bit output compare 4 ch. in0 to in5 in6/out2, in7/out3 out0, out1 external interrupt 8 ch. int0 to int7 a16 to a23 ad00 to ad15 tin0, tin1 tot0, tot1
mb90540/545 series 19 n n n n memory space the memory space of the mb90540/545 series is shown below. the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, the table in rom can be referenced without using the far spec- ification in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom.the rom area in bank ff exceeds 48 kbytes, and its entire image cannot be shown in bank 00.the image between ff4000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff3fff h is visible only in bank ff. mb90v540 mb90f543 mb90f549 ffffff h ff0000 h rom (ff bank) ffffff h ff0000 h rom (ff bank) ffffff h ff0000 h rom (ff bank) feffff h fe0000 h rom (fe bank) feffff h fe0000 h rom (fe bank) feffff h fe0000 h rom (fe bank) fdffff h fd0000 h rom (fd bank) external fdffff h fd0000 h rom (fd bank) fcffff h fc0000 h rom (fc bank) fcffff h fc0000 h rom (fc bank) external external 00ffff h 004000 h rom (image of ff bank) 00ffff h 004000 h rom (image of ff bank) 00ffff h 004000 h rom (image of ff bank) 003fff h 003900 h peripheral 003fff h 003900 h peripheral 003fff h 003900 h peripheral external 002000 h external 002000 h external 0020ff h 001ff5 h 001ff0 h rom correction 0018ff h 000100 h ram 6k 0018ff h 000100 h ram 6k 000100 h ram 8k external external external 0000bf h 000000 h peripheral 0000bf h 000000 h peripheral 0000bf h 000000 h peripheral
mb90540/545 series 20 n n n n i/o map (continued) address register abbreviation access peripheral initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx b 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 0a h port a data register pdra r/w port a _ _ _ _ _ _ _x b 0b h to 0f h reserved 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 b 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 b 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 b 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 b 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 b 15 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 b 16 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 b 17 h port 7 direction register ddr7 r/w port 7 0 0 0 0 0 0 0 0 b 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 b 19 h port 9 direction register ddr9 r/w port 9 0 0 0 0 0 0 0 0 b 1a h port a direction register ddra r/w port a _ _ _ _ _ _ _0 b 1b h analog input enable ader r/w port 6, a/d 1 1 1 1 1 1 1 1 b 1c h port 0 pullup control register pucr0 r/w port 0 0 0 0 0 0 0 0 0 b 1d h port 1 pullup control register pucr1 r/w port 1 0 0 0 0 0 0 0 0 b 1e h port 2 pullup control register pucr2 r/w port 2 0 0 0 0 0 0 0 0 b 1f h port 3 pullup control register pucr3 r/w port 3 0 0 0 0 0 0 0 0 b 20 h serial mode control register 0 umc0 r/w uart0 0 0 0 0 0 1 0 0 b 21 h serial status register 0 usr0 r/w 0 0 0 1 0 0 0 0 b 22 h serial input/output data register 0 uidr0/ uodr0 r/w xxxxxxxx b 23 h rate and data register 0 urd0 r/w 0 0 0 0 0 0 0x b
mb90540/545 series 21 (continued) address register abbreviation access peripheral initial value 24 h serial mode register 1 smr1 r/w uart1 0 0 0 0 0 0 0 0 b 25 h serial control register 1 scr1 r/w 0 0 0 0 0 1 0 0 b 26 h serial input/output data register 1 sidr1/ sodr1 r/w xxxxxxxx b 27 h serial status register 1 ssr1 r/w 0 0 0 0 1_0 0 b 28 h uart1 prescaler control register u1cdcr r/w 0_ _ _1 1 1 1 b 29 h edge selector ses1 r/w _ _ _ _ _ _ _0 b 2a h reserved 2b h serial io prescaler scdcr r/w serial io 0_ _ _1 1 1 1 b 2c h serial mode control register smcs r/w _ _ _ _0 0 0 0 b 2d h serial mode control register smcs r/w 0 0 0 0 0 0 1 0 b 2e h serial data register sdr r/w xxxxxxxx b 2f h edge selector ses2 r/w _ _ _ _ _ _ _0 b 30 h external interrupt enable register enir r/w external interrupt 0 0 0 0 0 0 0 0 b 31 h external interrupt request register eirr r/w xxxxxxxx b 32 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 33 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 34 h a/d control status register 0 adcs0 r/w a/d converter 0 0 0 0 0 0 0 0 b 35 h a/d control status register 1 adcs1 r/w 0 0 0 0 0 0 0 0 b 36 h a/d data register 0 adcr0 r xxxxxxxx b 37 h a/d data register 1 adcr1 r/w 0 0 0 0 1 _ xx b 38 h ppg0 operation mode control register ppgc0 r/w 16-bit programmable pulse generator 0/1 0 _ 0 0 0 _ _ 1 b 39 h ppg1 operation mode control register ppgc1 r/w 0 _ 0 0 0 0 0 1 b 3a h ppg0 and ppg1 clock select register ppg01 r/w 0 0 0 0 0 0 _ _ b 3b h reserved 3c h ppg2 operation mode control register ppgc2 r/w 16-bit programmable pulse generator 2/3 0 _ 0 0 0 _ _1 b 3d h ppg3 operation mode control register ppgc3 r/w 0 _ 0 0 0 0 0 1 b 3e h ppg2 and ppg3 clock select register ppg23 r/w 0 0 0 0 0 0 _ _ b 3f h reserved 40 h ppg4 operation mode control register ppgc4 r/w 16-bit programmable pulse generator 4/5 0 _ 0 0 0 _ _ 1 b 41 h ppg5 operation mode control register ppgc5 r/w 0 _ 0 0 0 0 0 1 b 42 h ppg4 and ppg5 clock select register ppg45 r/w 0 0 0 0 0 0 _ _ b 43 h reserved 44 h ppg6 operation mode control register ppgc6 r/w 16-bit programmable pulse generator 6/7 0 _ 0 0 0 _ _ 1 b 45 h ppg7 operation mode control register ppgc7 r/w 0 _ 0 0 0 0 0 1 b 46 h ppg6 and ppg7 output pin control register ppg67 r/w 0 0 0 0 0 0 _ _ b
mb90540/545 series 22 (continued) address register abbreviation access peripheral initial value 47 h to 4b h reserved 4c h input capture control status register 0/1 ics01 r/w input capture 0/1 0 0 0 0 0 0 0 0 b 4d h input capture control status register 2/3 ics23 r/w input capture 2/3 0 0 0 0 0 0 0 0 b 4e h input capture control status register 4/5 ics45 r/w input capture 4/5 0 0 0 0 0 0 0 0 b 4f h input capture control status register 6/7 ics67 r/w input capture 6/7 0 0 0 0 0 0 0 0 b 50 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 51 h timer control status register 0 tmcsr0 r/w _ _ _ _ 0 0 0 0 b 52 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 53 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 54 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 55 h timer control status register 1 tmcsr1 r/w _ _ _ _ 0 0 0 0 b 56 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 57 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 58 h output compare control status register 0 ocs0 r/w output compare 0/1 0 0 0 0 _ _ 0 0 b 59 h output compare control status register 1 ocs1 r/w _ _ _0 0 0 0 0 b 5a h output compare control status register 2 ocs2 r/w output compare 2/3 0 0 0 0 _ _ 0 0 b 5b h output compare control status register 3 ocs3 r/w _ _ _ 0 0 0 0 0 b 5c h to 6b h reserved 6c h timer data register tcdt r/w i/o timer 0 0 0 0 0 0 0 0 b 6d h timer data register tcdt r/w 0 0 0 0 0 0 0 0 b 6e h timer control register tccs r/w 0 0 0 0 0 0 0 0 b 6f h rom mirror register romm r/w rom mirror _ _ _ _ _ _ _ 1 b 70 h to 7f h reserved for can 0 interface. refer to can controller hardware manual 80 h to 8f h reserved for can 1 interface. refer to can controller hardware manual 90 h to 9d h reserved 9e h rom correction control status register pacsr r/w rom correction 0 0 0 0 0 0 0 0 b 9f h delayed interrupt/release register dirr r/w delayed interrupt _ _ _ _ _ _ _ 0 b a0 h low-power mode register lpmcr r/w low power controller 0 0 0 1 1 0 0 0 b a1 h clock selector register ckscr r/w low power controller 1 1 1 1 1 1 0 0 b a2 h to a4 h reserved
mb90540/545 series 23 (continued) address register abbreviation access peripheral initial value a5 h automatic ready function select register arsr w external memory access 0 0 1 1 _ _ 0 0 b a6 h external address output control register hacr w 0 0 0 0 0 0 0 0 b a7 h bus control signal select register ecsr w 0 0 0 0 0 0 0 _ b a8 h watchdog control register wdtc r/w watchdog timer xxxxx 1 1 1 b a9 h time base timer control tbtc r/w time base timer 1 - - 0 0 1 0 0 b aa h watch timer control register wtc r/w watch timer 1 x 0 0 0 0 0 0 b ab h to ad h reserved ae h flash control status register (flash only, otherwise reserved) fmcs r/w flash memory 0 0 0 x 0 _ _ 0 b af h reserved b0 h interrupt control register 00 icr00 r/w interrupt controller 0 0 0 0 0 1 1 1 b b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 b b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 b b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 b b4 h interrupt control register 04 icr04 r/w 0 0 0 0 0 1 1 1 b b5 h interrupt control register 05 icr05 r/w 0 0 0 0 0 1 1 1 b b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 b b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 b b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 b b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 b ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 b bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 b bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 b bd h interrupt control register 13 icr13 r/w 0 0 0 0 0 1 1 1 b be h interrupt control register 14 icr14 r/w 0 0 0 0 0 1 1 1 b bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 b co h to ff h external address register abbreviation access peripheral initial value 1ff0 h rom correction address 0 padr0 r/w rom correction xxxxxxxx b 1ff1 h rom correction address 1 padr0 r/w xxxxxxxx b 1ff2 h rom correction address 2 padr0 r/w xxxxxxxx b 1ff3 h rom correction address 3 padr1 r/w xxxxxxxx b 1ff4 h rom correction address 4 padr1 r/w xxxxxxxx b 1ff5 h rom correction address 5 padr1 r/w xxxxxxxx b
mb90540/545 series 24 (continued) address register abbreviation access peripheral initial value 3900 h reload l prll0 r/w 16-bit programmable pulse generator 0/1 xxxxxxxx b 3901 h reload h prlh0 r/w xxxxxxxx b 3902 h reload l prll1 r/w xxxxxxxx b 3903 h reload h prlh1 r/w xxxxxxxx b 3904 h reload l prll2 r/w 16-bit programmable pulse generator 2/3 xxxxxxxx b 3905 h reload h prlh2 r/w xxxxxxxx b 3906 h reload l prll3 r/w xxxxxxxx b 3907 h reload h prlh3 r/w xxxxxxxx b 3908 h reload l prll4 r/w 16-bit programmable pulse generator 4/5 xxxxxxxx b 3909 h reload h prlh4 r/w xxxxxxxx b 390a h reload l prll5 r/w xxxxxxxx b 390b h reload h prlh5 r/w xxxxxxxx b 390c h reload l prll6 r/w 16-bit programmable pulse generator 6/7 xxxxxxxx b 390d h reload h prlh6 r/w xxxxxxxx b 390e h reload l prll7 r/w xxxxxxxx b 390f h reload h prlh7 r/w xxxxxxxx b 3910 h to 3917 h reserved 3918 h input capture 0 ipcp0 r input capture 0/1 xxxxxxxx b 3919 h input capture 0 ipcp0 r xxxxxxxx b 391a h input capture 1 ipcp1 r xxxxxxxx b 391b h input capture 1 ipcp1 r xxxxxxxx b 391c h input capture 2 ipcp2 r input capture 2/3 xxxxxxxx b 391d h input capture 2 ipcp2 r xxxxxxxx b 391e h input capture 3 ipcp3 r xxxxxxxx b 391f h input capture 3 ipcp3 r xxxxxxxx b 3920 h input capture 4 ipcp4 r input capture 4/5 xxxxxxxx b 3921 h input capture 4 ipcp4 r xxxxxxxx b 3922 h input capture 5 ipcp5 r xxxxxxxx b 3923 h input capture 5 ipcp5 r xxxxxxxx b 3924 h input capture 6 ipcp6 r input capture 6/7 xxxxxxxx b 3925 h input capture 6 ipcp6 r xxxxxxxx b 3926 h input capture 7 ipcp7 r xxxxxxxx b 3927 h input capture 7 ipcp7 r xxxxxxxx b
mb90540/545 series 25 (continued) note initial value of _ represents unused bit, x represents unknown value. addresses in the range 0000 h to 00ff h , which are not listed in the table, are reserved for the primary functions of the mcu. a read access to these reserved addresses results in an x reading and any write access should not be performed. address register abbreviation access peripheral initial value 3928 h output compare 0 occp0 r/w output compare 0/1 xxxxxxxx b 3929 h output compare 0 occp0 r/w xxxxxxxx b 392a h output compare 1 occp1 r/w xxxxxxxx b 392b h output compare 1 occp1 r/w xxxxxxxx b 392c h output compare 2 occp2 r/w output compare 2/3 xxxxxxxx b 392d h output compare 2 occp2 r/w xxxxxxxx b 392e h output compare 3 occp3 r/w xxxxxxxx b 392f h output compare 3 occp3 r/w xxxxxxxx b 3930 h to 39ff h reserved 3a00 h to 3aff h reserved for can 0 interface. refer to can controller hardware manual 3b00 h to 3bff h reserved for can 0 interface. refer to can controller hardware manual 3c00 h to 3cff h reserved for can 1 interface. refer to can controller hardware manual 3d00 h to 3dff h reserved for can 1 interface. refer to can controller hardware manual 3e00 h to 3fff h reserved
mb90540/545 series 26 n n n n can controller the mb90540 series contains two can controllers (can0 and can1), the mb90545 series contains only one (can0). the evaluation chip mb90v540 also has two can controllers. the can controller has the following features: ? conforms to can specification version 2.0 part a and b - supports transmission/reception in standard frame and extended frame formats ? supports transmission of data frames by receiving remote frames ? 16 transmitting/receiving message buffers - 29-bit id and 8-byte data - multi-level message buffer configuration ? provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1d acceptance mask - two acceptance mask registers in either standard frame format or extended frame formats ? bit rate programmable from 10 kbit/s to 1 mbit/s (when input clock is at 16 mhz) list of control registers address register abbreviation access initial value can0 can1 000070 h 000080 h message buffer valid register bvalr r/w 00000000 00000000 b 000071 h 000081 h 000072 h 000082 h transmit request register treqr r/w 00000000 00000000 b 000073 h 000083 h 000074 h 000084 h transmit cancel register tcanr w 00000000 00000000 b 000075 h 000085 h 000076 h 000086 h transmit complete register tcr r/w 00000000 00000000 b 000077 h 000087 h 000078 h 000088 h receive complete register rcr r/w 00000000 00000000 b 000079 h 000089 h 00007a h 00008a h remote request receiving register rrtrr r/w 00000000 00000000 b 00007b h 00008b h 00007c h 00008c h receive overrun register rovrr r/w 00000000 00000000 b 00007d h 00008d h 00007e h 00008e h receive interrupt enable register rier r/w 00000000 00000000 b 00007f h 00008f h
mb90540/545 series 27 list of control registers address register abbreviation access initial value can0 can1 003b00 h 003d00 h control status register csr r/w, r 00---000 0----0-1 b 003b01 h 003d01 h 003b02 h 003d02 h last event indicator register leir r/w -------- 000-0000 b 003b03 h 003d03 h 003b04 h 003d04 h receive/transmit error counter rtec r 00000000 00000000 b 003b05 h 003d05 h 003b06 h 003d06 h bit timing register btr r/w -1111111 11111111 b 003b07 h 003d07 h 003b08 h 003d08 h ide register ider r/w xxxxxxxx xxxxxxxx b 003b09 h 003d09 h 003b0a h 003d0a h transmit rtr register trtrr r/w 00000000 00000000 b 003b0b h 003d0b h 003b0c h 003d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx xxxxxxxx b 003b0d h 003d0d h 003b0e h 003d0e h transmit interrupt enable reg- ister tier r/w 00000000 00000000 b 003b0f h 003d0f h 003b10 h 003d10 h acceptance mask select regis- ter amsr r/w xxxxxxxx xxxxxxxx b 003b11 h 003d11 h 003b12 h 003d12 h xxxxxxxx xxxxxxxx b 003b13 h 003d13 h 003b14 h 003d14 h acceptance mask register 0 amr0 r/w xxxxxxxx xxxxxxxx b 003b15 h 003d15 h 003b16 h 003d16 h xxxxx--- xxxxxxxx b 003b17 h 003d17 h 003b18 h 003d18 h acceptance mask register 1 amr1 r/w xxxxxxxx xxxxxxxx b 003b19 h 003d19 h 003b1a h 003d1a h xxxxx--- xxxxxxxx b 003b1b h 003d1b h
mb90540/545 series 28 list of message buffers (id registers) (1) address register abbreviation access initial value can0 can1 003a00 h to 003a1f h 003c00 h to 003c1f h general-purpose ram ? r/w xxxxxxxx b to xxxxxxxx b 003a20 h 003c20 h id register 0 idr0 r/w xxxxxxxx xxxxxxxx b 003a21 h 003c21 h 003a22 h 003c22 h xxxxx--- xxxxxxxx b 003a23 h 003c23 h 003a24 h 003c24 h id register 1 idr1 r/w xxxxxxxx xxxxxxxx b 003a25 h 003c25 h 003a26 h 003c26 h xxxxx--- xxxxxxxx b 003a27 h 003c27 h 003a28 h 003c28 h id register 2 idr2 r/w xxxxxxxx xxxxxxxx b 003a29 h 003c29 h 003a2a h 003c2a h xxxxx--- xxxxxxxx b 003a2b h 003c2b h 003a2c h 003c2c h id register 3 idr3 r/w xxxxxxxx xxxxxxxx b 003a2d h 003c2d h 003a2e h 003c2e h xxxxx--- xxxxxxxx b 003a2f h 003c2f h 003a30 h 003c30 h id register 4 idr4 r/w xxxxxxxx xxxxxxxx b 003a31 h 003c31 h 003a32 h 003c32 h xxxxx--- xxxxxxxx b 003a33 h 003c33 h 003a34 h 003c34 h id register 5 idr5 r/w xxxxxxxx xxxxxxxx b 003a35 h 003c35 h 003a36 h 003c36 h xxxxx--- xxxxxxxx b 003a37 h 003c37 h 003a38 h 003c38 h id register 6 idr6 r/w xxxxxxxx xxxxxxxx b 003a39 h 003c39 h 003a3a h 003c3a h xxxxx--- xxxxxxxx b 003a3b h 003c3b h
mb90540/545 series 29 list of message buffers (id registers) (2) address register abbreviation access initial value can0 can1 003a3c h 003c3c h id register 7 idr7 r/w xxxxxxxx xxxxxxxx b 003a3d h 003c3d h 003a3e h 003c3e h xxxxx--- xxxxxxxx b 003a3f h 003c3f h 003a40 h 003c40 h id register 8 idr8 r/w xxxxxxxx xxxxxxxx b 003a41 h 003c41 h 003a42 h 003c42 h xxxxx--- xxxxxxxx b 003a43 h 003c43 h 003a44 h 003c44 h id register 9 idr9 r/w xxxxxxxx xxxxxxxx b 003a45 h 003c45 h 003a46 h 003c46 h xxxxx--- xxxxxxxx b 003a47 h 003c47 h 003a48 h 003c48 h id register 10 idr10 r/w xxxxxxxx xxxxxxxx b 003a49 h 003c49 h 003a4a h 003c4a h xxxxx--- xxxxxxxx b 003a4b h 003c4b h 003a4c h 003c4c h id register 11 idr11 r/w xxxxxxxx xxxxxxxx b 003a4d h 003c4d h 003a4e h 003c4e h xxxxx--- xxxxxxxx b 003a4f h 003c4f h 003a50 h 003c50 h id register 12 idr12 r/w xxxxxxxx xxxxxxxx b 003a51 h 003c51 h 003a52 h 003c52 h xxxxx--- xxxxxxxx b 003a53 h 003c53 h 003a54 h 003c54 h id register 13 idr13 r/w xxxxxxxx xxxxxxxx b 003a55 h 003c55 h 003a56 h 003c56 h xxxxx--- xxxxxxxx b 003a57 h 003c57 h 003a58 h 003c58 h id register 14 idr14 r/w xxxxxxxx xxxxxxxx b 003a59 h 003c59 h 003a5a h 003c5a h xxxxx--- xxxxxxxx b 003a5b h 003c5b h 003a5c h 003c5c h id register 15 idr15 r/w xxxxxxxx xxxxxxxx b 003a5d h 003c5d h 003a5e h 003c5e h xxxxx--- xxxxxxxx b 003a5f h 003c5f h
mb90540/545 series 30 list of message buffers (dlc registers and data registers) (1) address register abbreviation access initial value can0 can1 003a60 h 003c60 h dlc register 0 dlcr0 r/w ----xxxx b 003a61 h 003c61 h 003a62 h 003c62 h dlc register 1 dlcr1 r/w ----xxxx b 003a63 h 003c63 h 003a64 h 003c64 h dlc register 2 dlcr2 r/w ----xxxx b 003a65 h 003c65 h 003a66 h 003c66 h dlc register 3 dlcr3 r/w ----xxxx b 003a67 h 003c67 h 003a68 h 003c68 h dlc register 4 dlcr4 r/w ----xxxx b 003a69 h 003c69 h 003a6a h 003c6a h dlc register 5 dlcr5 r/w ----xxxx b 003a6b h 003c6b h 003a6c h 003c6c h dlc register 6 dlcr6 r/w ----xxxx b 003a6d h 003c6d h 003a6e h 003c6e h dlc register 7 dlcr7 r/w ----xxxx b 003a6f h 003c6f h
mb90540/545 series 31 list of message buffers (dlc registers and data registers) (2) address register abbreviation access initial value can0 can1 003a70 h 003c70 h dlc register 8 dlcr8 r/w ----xxxx 003a71 h 003c71 h 003a72 h 003c72 h dlc register 9 dlcr9 r/w ----xxxx b 003a73 h 003c73 h 003a74 h 003c74 h dlc register 10 dlcr10 r/w ----xxxx b 003a75 h 003c75 h 003a76 h 003c76 h dlc register 11 dlcr11 r/w ----xxxx b 003a77 h 003c77 h 003a78 h 003c78 h dlc register 12 dlcr12 r/w ----xxxx b 003a79 h 003c79 h 003a7a h 003c7a h dlc register 13 dlcr13 r/w ----xxxx b 003a7b h 003c7b h 003a7c h 003c7c h dlc register 14 dlcr14 r/w ----xxxx b 003a7d h 003c7d h 003a7e h 003c7e h dlc register 15 dlcr15 r/w ----xxxx b 003a7f h 003c7f h 003a80 h to 003a87 h 003c80 h to 003c87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b 003a88 h to 003a8f h 003c88 h to 003c8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 003a90 h to 003a97 h 003c90 h to 003c97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 003a98 h to 003a9f h 003c98 h to 003c9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 003aa0 h to 003aa7 h 003ca0 h to 003ca7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 003aa8 h to 003aaf h 003ca8 h to 003caf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 003ab0 h to 003ab7 h 003cb0 h to 003cb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b
mb90540/545 series 32 list of message buffers (dlc registers and data registers) (3) address register abbreviation access initial value can0 can1 003ab8 h to 003abf h 003cb8 h to 003cbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 003ac0 h to 003ac7 h 003cc0 h to 003cc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 003ac8 h to 003acf h 003cc8 h to 003ccf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 003ad0 h to 003ad7 h 003cd0 h to 003cd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 003ad8 h to 003adf h 003cd8 h to 003cdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 003ae0 h to 003ae7 h 003ce0 h to 003ce7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 003ae8 h to 003aef h 003ce8 h to 003cef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b 003af0 h to 003af7 h 003cf0 h to 003cf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 003af8 h to 003aff h 003cf8 h to 003cff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
mb90540/545 series 33 n n n n interrupt map interrupt cause ei 2 os clear interrupt vector interrupt control register number address number address reset n/a #08 ffffdc h ?? int9 instruction n/a #09 ffffd8 h ?? exception n/a #10 ffffd4 h ?? can 0 rx n/a #11 ffffd0 h icr00 0000b0 h can 0 tx/ns n/a #12 ffffcc h can 1 rx n/a #13 ffffc8 h icr01 0000b1 h can 1 tx/ns n/a #14 ffffc4 h external interrupt int0/int1 *1 #15 ffffc0 h icr02 0000b2 h time base timer n/a #16 ffffbc h 16-bit reload timer 0 *1 #17 ffffb8 h icr03 0000b3 h 8/10-bit a/d converter *1 #18 ffffb4 h i/o timer n/a #19 ffffb0 h icr04 0000b4 h external interrupt int2/int3 *1 #20 ffffac h serial i/o *1 #21 ffffa8 h icr05 0000b5 h 8/16-bit ppg 0/1 n/a #22 ffffa4 h input capture 0 *1 #23 ffffa0 h icr06 0000b6 h external interrupt int4/int5 *1 #24 ffff9c h input capture 1 *1 #25 ffff98 h icr07 0000b7 h 8/16-bit ppg 2/3 n/a #26 ffff94 h external interrupt int6/int7 *1 #27 ffff90 h icr08 0000b8 h watch timer n/a #28 ffff8c h 8/16-bit ppg 4/5 n/a #29 ffff88 h icr09 0000b9 h input capture 2/3 *1 #30 ffff84 h 8/16-bit ppg 6/7 n/a #31 ffff80 h icr10 0000ba h output compare 0 *1 #32 ffff7c h output compare 1 *1 #33 ffff78 h icr11 0000bb h input capture 4/5 *1 #34 ffff74 h output compare 2/3 - input capture 6/7 *1 #35 ffff70 h icr12 0000bc h 16-bit reload timer 1 *1 #36 ffff6c h uart 0 rx *2 #37 ffff68 h icr13 0000bd h uart 0 tx *1 #38 ffff64 h uart 1 rx *2 #39 ffff60 h icr14 0000be h uart 1 tx *1 #40 ffff5c h flash memory n/a #41 ffff58 h icr15 0000bf h delayed interrupt n/a #42 ffff54 h
mb90540/545 series 34 *1: the interrupt request flag is cleared by the ei 2 os interrupt clear signal. *2: the interrupt request flag is cleared by the ei 2 os interrupt clear signal. a stop request is available. n/a:the interrupt request flag is not cleared by the ei 2 os interrupt clear signal. note: for a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the ei 2 os interrupt clear signal. at the end of ei 2 os, the ei 2 os clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. if one interrupt flag starts the ei 2 os and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the ei 2 os clear signal caused by the first event. so it is recommended not to use the ei 2 os for this interrupt number. if ei 2 os is enabled, ei 2 os is initiated when one of the two interrupt signals in the same interrupt control register (icr) is asserted. this means that different interrupt sources share the same ei 2 os descriptor which should be unique for each interrupt source. for this reason, when one interrupt source uses the ei 2 os, the other interrupt should be disabled.
mb90540/545 series 35 n n n n electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0v) *1: av cc , avrl and avrl should not exceed v cc , and avrl should not exceed avrh. *2: v i and v o should not exceed v cc + 0.3v. v i should not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supercedes the v i rating. *3: the maximum output current is a peak value for a corresponding pin. *4: average output current is an average current value observed for a 100 ms period for a corresponding pin. *5: total average current is an average current value observed for a 100 ms period for all corresponding pins. note: average output current = operating current operating efficiency warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value units remarks min. max. power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 avrh, avrl v ss - 0.3 v ss + 6.0 v av cc 3 avrh/avrl, avrh 3 avrl *1 input voltage v i v ss - 0.3 v ss + 6.0 v *2 output voltage v o v ss - 0.3 v ss + 6.0 v *2 clamp current i clamp - 2.0 2.0 ma "l" level max. output current i ol ? 15 ma *3 "l" level avg. output current i olav ? 4ma *4 "l" level max. overall output current ? i ol ? 100 ma "l" level avg. overall output current ? i olav ? 50 ma *5 "h" level max. output current i oh ?- 15 ma *3 "h" level avg. output current i ohav ?- 4ma *4 "h" level max. overall output current ? i oh ?- 100 ma "h" level avg. overall output current ? i ohav ?- 50 ma *5 power consumption p d ? 500 mw mb90f543/f549 operating temperature t a - 40 + 85 c storage temperature t stg - 55 + 150 c
mb90540/545 series 36 2. recommended conditions (v ss = av ss = 0v) *: use a ceramic capacitor or a capacitor of better ac characteristics. the v cc capacitor should be greater than this capacitor. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value units remarks min. typ. max. power supply voltage v cc 4.5 5.0 5.5 v smooth capacitor c s 0.022 0.1 1.0 m f* operating temperature t a - 40 + 85 c c c s ? c pin connection diagram
mb90540/545 series 37 3. dc characteristics (v cc = 5.0 v 10%, v ss = av ss = 0v, t a = - 40 c to + 85 c) *: current values are tentative. they are subject to change without notice according to improvements in the characteristics. the power supply current testing conditions are when using the external clock. parame- ter sym bol pin condition value units remarks min. typ. max. input h voltage v ihs cmos hys- teresis input pin ? 0.8 v cc ? v cc + 0.3 v v ihm md input pin ? v cc - 0.3 ? v cc + 0.3 v input l voltage v ils cmos hys- teresis input pin ? v cc - 0.3 ? 0.2 v cc v v ilm md input pin ? v cc - 0.3 ? v cc + 0.3 v output h voltage v oh all output pins v cc = 4.5v, i oh = - 4.0ma v cc C 0.5 v output l voltage v ol all output pins v cc = 4.5v, i ol = 4.0ma 0.4v input leak current i il v cc = 5.5v, v ss < v i < v cc C5 5 m a power supply current* i cc v cc v cc = 5.0 v 10%, internal frequency: 16 mhz, at normal operation 45 60 ma mb90f543/f549 i ccs v cc = 5.0v 10%, internal frequency: 16 mhz, at sleep 13 22 ma mb90f543/f549 i ccl v cc = 5.0v, internal frequency: 8 khz, at sub operation 0.2 1 ma mb90f543/f549 i ccls v cc = 5.0v, internal frequency: 8 khz, at sub sleep 1050 m a mb90f543/f549 i cct v cc = 5.0v, internal frequency: 8 khz, at watch mode 1050 m a mb90f543/f549 i cch1 v cc = 5.0 v 10%, at stop, t a = 25 c 520 m a mb90f543/f549 i cch2 v cc = 5.0 v 10%, at hardware standby mode, t a = 25 c 50100 m a mb90f543/f549 input capacity c in other than av cc , av ss , avrh, avrl, c, v cc , v ss 10 80 pf
mb90540/545 series 38 4. ac characteristics (1) clock timing (v cc = 5.0 v 10%, v ss = av ss = 0 v, t a = - 40 c to + 85 c) * : frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock. parameter symbol pin value units remarks min. typ. max. oscillation frequency f c x0, x1 3 16 mhz f cl x0a, x1a 32.768 khz oscillation cycle time t cyl x0, x1 62.5 333 ns t lcyl x0a, x1a 30.5 m s frequency deviation with pll * d f5% input clock pulse width p wh , p wl x0 10 ns duty ratio is about 30 to 70%. p wlh ,p wll x0a 15.2 m s input clock rise and fall time t cr , t cf x0 5 ns when using external clock machine clock frequency f cp 1.5 16 mhz when using main clock f lcp 8.192 khz when using sub-clock machine clock cycle time t cp 62.5 666 ns when using main clock t lcp 122.1 m s when using sub-clock + a c en t r al f r eq uenc y f o - a d f a fo ------ 100% = t cyl p wh t cf p wl t cr 0.8 v cc 0.2 v cc x0 t lcyl p wlh t cf p wll t cr 0.8 v cc 0.2 v cc x0a ? clock timing
mb90540/545 series 39 ac characteristics are set to the measured reference voltage values below. 16 5.5 4.5 3.3 3.0 1.5 3 8 12 power supply voltage v cc (v) machine clock f cp (mhz) guaranteed operation range for mb90f543/f549 guaranteed operation range of mb90v540 guaranteed pll operation range ? guaranteed operation range 16 12 4 9 8 3 4 8 16 machine clock f cp (mhz) oscillation clock f c (mhz) ? oscillation clock frequency and machine clock frequency 4 3 2 1 1/2 (pll off) tb d ? input signal waveform hysteresis input pin 0.8 v cc 0.2 v cc ? output signal waveform output pin 2.4 v 0.8 v
mb90540/545 series 40 (2) clock output timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) (3) reset and hardware standby input (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) t cp represents one cycle time of the machine clock. any reset can not fully initialize the flash memory if it is performing the automatic algorithm. parameter symbol pin condition value units remarks min. max. cycle time t cyc clk v cc = 5 v 10% 62.5 ns clk - t clk t chcl 20 ns parameter symbol pin value units remarks min. max. reset input time t rstl rst 16 t cp ns hardware standby input time t hstl hst 16 t cp ns t cyc t chcl 2.4 v 0.8 v clk 2.4 v 0.2 v cc rst hst t rstl , t hstl 0.2 v cc
mb90540/545 series 41 (4) power on reset (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = - 40 c to + 85 c) note v cc must be kept lower than 0.2 v before power-on. the above values are used for creating a power-on reset. some registers in the device are initialized only upon a power-on reset. to initialize these register, turn on the power supply using the above values. parameter symbol pin condition value units remarks min. max. power on rise time t r v cc 0.05 30 ms power off time t off v cc 50 ms due to repetitive operation t r 2.7 v 0.2 v v cc 0.2 v 0.2 v t off sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 v or fewer per second, however, you can use the pll clock. v cc v ss tbd ram data being held it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower.
mb90540/545 series 42 (5) bus timing (read) (v cc = 4.5 v to 5.5 v, v ss = 0 v, t a = - 40 c to + 85 c) parameter symbol pin condition value units remarks min. max. ale pulse width t lhll ale t cp /2 - 20 ns valid address t ale time t avll ale, a23 to a16, ad15 to ad00 t cp /2 - 20 ns ale t address valid time t llax ale, ad15 to ad00 t cp /2 - 15 ns valid address t rd time t avrl a23 toa16, ad15 to ad00, rd t cp - 15 ns valid address t valid data input t avdv a23 to a16, ad15 to ad00 5 t cp /2 - 60 ns rd pulse width t rlrh rd 3 t cp /2 - 20 ns rd t valid data input t rldv rd , ad15 to ad00 3 t cp /2 - 60 ns rd - t data hold time t rhdx rd , ad15 to ad00 0ns rd t ale - time t rhlh rd , ale t cp /2 - 15 ns rd - t address valid time t rhax rd , a23 to a16 t cp /2 - 10 ns valid address t clk - time t avch a23 to a16, ad15 to ad00, clk t cp /2 - 20 ns rd t clk - time t rlch rd , clk t cp /2 - 20 ns ale t rd time t llrl ale, rd t cp /2 - 15 ns
mb90540/545 series 43 clk t avch 2.4 v t rlch 2.4 v ale 2.4 v t lhll 2.4 v t rhlh 0.8 v t llax 2.4 v t avll rd t llrl t rlrh 0.8 v 2.4 v t avrl a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t rhax ad15 to ad00 0.8 v 2.4 v 2.4 v 0.8 v address 0.2 v cc 0.8 v cc 0.8 v cc 0.2 v cc read data t rhdx t rldv t avdv ? bus timing (read)
mb90540/545 series 44 (6) bus timing (write) (v cc = 4.5 v to 5.5 v, v ss = 0 v, t a = - 40 c to + 85 c) parameter symbol pin condition value units remarks min. max. valid address t wr time t avwl a23 to a16, ad15 to ad00, wr t cp C 15 ns wr pulse width t wlwh wr 3 t cp /2 C 20 ns valid data output t wr - time t dvwh ad15 to ad00, wr 3 t cp /2 C 20 ns wr - t data hold time t whdx ad15 to ad00, wr 20 ns wr - t address valid time t whax a23 to a16, wr t cp /2 C 10 ns wr - t ale - time t whlh wr , ale t cp /2 C 15 ns wr t clk - time t wlch wr , clk t cp /2 C 20 ns clk t wlch 2.4 v ale t whlh 2.4 v wr (wrl , wrh ) t wlwh 0.8 v 2.4 v t avwl a23 to a16 0.8 v 2.4 v 2.4 v 0.8 v t whax ad15 to ad00 2.4 v 0.8 v address 0.8 v 2.4 v write data t dvwh 0.8 v 2.4 v t whdx ? bus timing (write)
mb90540/545 series 45 (7) ready input timing (v cc = 4.5 v to 5.5 v, v ss = 0 v, t a = - 40 c to + 85 c) note: if the rdy setup time is insufficient, use the auto-ready function. parameter symbol pin condition value units remarks min. max. rdy setup time t ryhs rdy 45 ns rdy hold time t ryhh rdy 0 ns clk 2.4 v ale rd /wr rdy no wait is used. 0.8 v cc 0.8 v cc t ryhh rdy when wait is used (1 cycle). t ryhs 0.2 v cc ? ready input timing
mb90540/545 series 46 (8) hold timing (v cc = 4.5 v to 5.5 v, v ss = 0 v, t a = - 40 c to + 85 c) note: there is more than 1 cycle from the time hrq is read to the time the hak is changed. (9) uart0/1, serial i/o timing (v cc = 4.5 v to 5.5 v, v ss = 0 v, t a = C40 c to + 85 c) note: 1.ac characteristic in clk synchronized mode. 2. c l is load capacity value of pins when testing. 3. t cp is the machine cycle (unit: ns). parameter symbol pin condition value units remarks min. max. pin floating t hak time t xhal hak 30 t cp ns hak - time t pin valid time t hahv hak t cp 2 t cp ns parameter symbol pin symbol condition value units remarks min. max. serial clock cycle time t scyc sck0 to sck2 internal clock opera- tion output pins are c l = 80 pf + 1 ttl. 8 t cp ns sck t sot delay time t slov sck0 to sck2, sot0 to sot2 C80 80 ns valid sin t sck - t ivsh sck0 to sck2, sin0 to sin2 100 ns sck - t valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ns serial clock "h" pulse width t shsl sck0 to sck2 external clock oper- ation output pins are c l = 80 pf + 1 ttl. 4 t cp ns serial clock "l" pulse width t slsh sck0 to sck2 4 t cp ns sck t sot delay time t slov sck0 to sck2, sot0 to sot2 150 ns valid sin t sck - t ivsh sck0 to sck2, sin0 to sin2 60 ns sck - t valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ns hak each pin high impedance t hahv t xhal 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v ? hold timing
mb90540/545 series 47 sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin 0.2 v cc 0.8 v cc t ivsh 0.2 v cc 0.8 v cc t shix ? internal shift clock mode sck 0.8 v cc t slsh 0.2 v cc sot 0.8 v 2.4 v t slov sin 0.2 v cc 0.8 v cc t ivsh 0.2 v cc 0.8 v cc t shix 0.8 v cc 0.2 v cc t shsl ? external shift clock mode
mb90540/545 series 48 (10) timer related resource input timing (v cc = 4.5 v to 5.5 v, v ss = 0 v, t a = - 40 c to + 85 c) (11) timer related resource output timing (v cc = 4.5 v to 5.5 v, v ss = 0 v, t a = - 40 c to + 85 c) parameter symbol pin condition value units remarks min. max. input pulse width t tiwh tin0, tin1 4 t cp ns t tiwl in0 to in7 parameter symbol pin condition value units remarks min. max. clk - t t out change time t to tot0 to tot1, ppg0 to ppg3 30ns 0.2 v cc 0.8 v cc t tiwh 0.2 v cc 0.8 v cc t tiwl ? timer input timing clk 2.4 v t out 0.8 v 2.4 v t to ? timer output timing
mb90540/545 series 49 (12) trigger input timing (v cc = 4.5 to 5.5 v, v ss = 0 v, t a = C40 c to + 85 c) parameter symbol pin condition value units remarks min. max. input pulse width t trgh t trgl int0 to int7, adtg 5 t cp ns 0.2 v cc 0.8 v cc t trgh 0.2 v cc 0.8 v cc t trgl ? trigger input timing
mb90540/545 series 50 5. a/d converter ( v cc = av cc = 5.0 v 10%, v ss = av ss = 0 v,3.0 v avrh - avrl, t a = - 40 c to +85 c) *: when not using an a/d converter, this is the current (v cc = av cc = avrh = 5.0 v) when the cpu is stopped. parameter symbol pin rated value units remarks min. typ. max. resolution 10 bit conversion error 5.0 lsb nonlinearity error 2.5 lsb differential nonlinearity error 1.9 lsb zero reading voltage v ot an0 to an7 avrl - 3.5 avrl + 0.5 avrl + 4.5 mv full scale reading voltage v fst an0 to an7 avrh - 6.5 avrh - 1.5 avrh + 1.5 mv conversion time 352t cp ns sampling time 64t cp ns analog port input current i ain an0 to an7 - 10 10 m a analog input voltage range v ain an0 to an7 avrl avrh v reference voltage range avrh avrl + 2.7 av cc v avrl 0 avrh - 2.7 v power supply current i a av cc 5ma i ah av cc 5 m a* reference voltage current i r avrh 200 400 600 m a i rh avrh 5 m a* offset between input channels an0 to an7 4 lsb
mb90540/545 series 51 6. a/d converter glossary resolution: analog changes that are identifiable with the a/d converter linearity error: the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics differential linearity error: the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value total error: the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. (continued) total error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh actual conversion value d i g i t a l o u t p u t v nt (measured value) 0.5 lsb actual conversion characteristics theoretical characteristics 0.5 lsb {1 lsb (n C 1) + 0.5 lsb} [v] avrh C avrl 1024 1 lsb = (theoretical value) v ot (theoretical value) = avrl + 0.5 lsb[v] v fst (theoretical value) = avrh C 1.5 lsb[v] total error for digital output n [lsb] v nt C {1 lsb (n C 1) + 0.5 lsb} 1 lsb = v nt : voltage at a transition of digital output from (n C 1) to n
mb90540/545 series 52 (continued) 7. notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions, : ? output impedance values of the external circuit of 15 k w or lower are recommended. ? when capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. when the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 m s @machine clock of 16 mhz). ?error the smaller the | avrh - avrl |, the greater the error would become relatively. linearity error 3ff 3fe 3fd 004 003 002 001 analog input avrl avrh analog input avrl avrh actual conversion characteristics v ot (measured value) v fst (measured value) actual conversion value v nt {1 lsb (n C 1)+ v ot } theoretical characteristics d i g i t a l o u t p u t d i g i t a l o u t p u t differential linearity error theoretical characteristics v (n + 1)t (measured value) actual conversion value v nt (measured value) actual conversion value linearity error of digital output n v ot: voltage at transition of digital output from 000 h to 001 h v fst : voltage at transition of digital output from 3fe h to 3ff h [lsb] v nt C {1 lsb (n C 1) + v ot } 1 lsb = [v] v fst C v ot 1022 = 1 lsb C 1 lsb [lsb] v (n + 1)t C v nt 1 lsb = differential linearity error of digital n n + 1 n n C 1 n C 2 ? equipment of analog input circuit model note: listed values must be considered as standards. comparator analog input c 0 c 1
mb90540/545 series 53 n n n n ordering information part number package remarks mb90f543pf MB90F549PF 100-pin plastic qfp (fpt-100p-m06) mb90v540cr 256-pin ceramic pga (pga-256c-a01) for evaluation
mb90540/545 series 54 n n n n package dimensions 100-pin plastic qfp (fpt-100p-m06) dimensions in mm (inches) c 2000 fujitsu limited f100008-3c-3 "a" "b" 0.53(.021)max 0.18(.007)max details of "a" part 0 10 details of "b" part 12.35(.486) ref 16.30?.40 (.642?016) 0.05(.002)min (stand off) 0.15?.05(.006?002) index 23.90?.40(.941?016) 20.00?.20(.787?008) 17.90?.40 14.00?.20 (.551?008) (.705?016) 0.13(.005) m 18.85(.742)ref 22.30?.40(.878?016) 1 30 31 50 51 80 81 100 0.25(.010) 0.30(.012) 0.65(.0256)typ 0.30?.10 (.012?004) lead no. 0.80?.20 (.031?008) 3.35(.132)max (mounting height) 0.10(.004)
mb90540/545 series 55 250-pin ceramic pga (pga-256c-a01) dimensions in mm (inches) index area 25.10 ?0.30 (.988 ?.012) sq c1.02 (.040) typ c0.51 (.020) typ (3 plcs) 0.20 ?0.05 (.0079 ?.002) 22.86 (.900) ref 1.27 (.050) typ 1.50 + 0.30 ?0.10 (.059 ) + .012 ?.004 6.35 (.250) max extra index pin 1994 fujitsu limited r256001sc-5-3 c
mb90540/545 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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